This invention is in the field of integrated circuits, and is more specifically directed to clock synthesis circuits for generating periodic signals of selected frequency and phase for use in integrated circuits.
As is fundamental in the art, many modem electronic systems now include numerous integrated circuits that operate in conjunction with one another. In complex high performance systems such as modern personal computers and workstations, these integrated circuits are synchronized with a system clock. In consumer-oriented systems such as televisions and home theaters, for example, system operation is synchronized with respect to a synchronization pulse that is included within the display signal itself. In these and other electronic systems, the generation of periodic signals for clocking the operation of circuit functions based upon a system clock or synchronization pulse, is a common and often critical function.
A conventional approach for generating periodic signals based upon a reference clock utilizes the well-known phase-locked loop, or PLL. In general, PLL circuits operate by comparing the time at which an edge of a reference clock is received relative to a corresponding edge of an internally generated clock. If a significant delay between these two edges is detected, the generation of the internal clock is adjusted to more closely match the received reference clock. In conventional analog PLLs, the frequency of a voltage controlled oscillator is adjusted by a filtered signal from a phase detector that compares system and chip clocks, so that the instantaneous frequency of the internal chip clock is advanced or retarded depending upon whether the chip clock lags or leads the system clock. Analog PLLs therefore adjust the phase of the chip clock in a substantially continuous manner in response to a phase difference between the internal chip clock and the system clock. This smooth operation generally depends upon the filtering of the output of the phase detector circuit, but can be made quite well-behaved in most implementations. Additionally, by inserting frequency dividers in the forward and feedback loops, analog PLLs can be used to generate periodic signals of a selectable frequency multiple of the input reference clock.
Modern digital integrated circuits generally use digital circuitry to generate multiple internal chip clocks that are based upon the output of a PLL. However, these digitally-generated clock signals can only be adjusted to a discrete accuracy that corresponds to the minimum step size of the digital clock generation circuitry. This incremental change in phase is often noticeable, particularly at high frequencies. The resulting “phase jitter” is now a commonly specified parameter for digital clock circuitry, as this effect is often a limiting factor in the accuracy and performance of the circuit.
In addition to phase jitter, the performance of PLL-based clock circuits in response to phase drift is another important parameter. Phase drift, which refers to the variation in the phase of a generated clock relative to the reference clock over time, can be caused by the accumulation of error over a number of clock cycles. Additionally, phase drift can also be caused by temperature and power supply voltage variations, and system noise.
Certain applications of clock generation circuitry are more sensitive to one of these parameters than to the other. A particularly difficult circuit application of clock generation circuitry is the video decoding of television signals (transmitted or recorded) into digital data for computer display or digital video processing. As is well known in the art, conventional television signals included a synchronization pulse at the beginning of each scan line; in the case of a broadcast signal, this synchronization pulse is transmitted, while in the case of a video tape, the synchronization pulse is part of the recorded information. Color information is communicated within each scan line by way of the phase relationship of the color burst signal for each horizontal display location to the synchronization pulse. In order to achieve the desired accuracy in the displayed image, a video decoder system must be able to resolve relatively small phase variations (e.g., on the order of 10□) in the color burst signal which occur at relatively long times (e.g., as long as 160 μsec after a 16 MHz synchronization pulse). In order to carry out the desired video decoding of such a signal, the video decoder must be capable of generating a clock signal that has very little drift over time, for example with as little as 1 nsec drift over 160 μsec.
Known clock generator circuits based on a phase-locked loop (PLL) are described in Mair and Xiu, “An Architecture of High-Performance Frequency and Phase Synthesis”, J. Solid State Circ., Vo. 35, No. 16 (IEEE, June, 2000), pp. 835-46, and in copending and commonly assigned application Ser. No. 09/472,268, filed Dec. 27, 1999, both incorporated herein by this reference. In this clock circuit, the voltage controlled oscillator (VCO) of the PLL produces a plurality of evenly-spaced output phases, each at frequency that is locked to a reference clock. A register stores a digital value that selects the desired phase to be applied to the clock input of a toggle flip-flop from which the output clock is generated. A frequency synthesis circuit adds integer and fraction portions of an incoming frequency selection value to the current contents of the register. The fraction portion of the frequency selection value permits a time-averaged clock frequency to be produced with more precision than would be attained by the integer portions selecting the multiple VCO output phases. This article also describes alternative realizations, including multiple frequency synthesis circuits based upon the same PLL (25), and the generation of a phase-shifted secondary output from a phase synthesis circuit that is slaved to the frequency synthesis circuit. Additional performance is obtained by providing separate paths for producing the leading and trailing edges of the output clock.
FIG. 1 illustrates an example of one of the frequency synthesis circuits described in the Mair and Xiu article. In FIG. 1, clock generation circuit 122 includes PLL 125, frequency synthesis circuit 127 for generating a clock signal on line COUT that is at a selected frequency, and phase synthesis circuit 129 for generating a second clock signal on line CSHOUT that is in a fixed phase relationship, and identical frequency, with the clock signal on line COUT. In frequency synthesis circuit 127, thirty-two equally spaced clock phases generated by a VCO in PLL 125 are received at inputs of multiplexer 134. The selected one of the clock phases indicated by select lines SEL appears at the output of multiplexer 134 and is applied to the clock input of D-type flip-flop 136, which is connected in toggle fashion. This inverting output of flip-flop 136 drives the output clock signal on line COUT.
The selection of clock phases by multiplexer 134 according to this preferred embodiment of the invention is determined by an input value presented on lines FREQ, which include both an integer portion and a fractional portion, and is applied to one input of adder 138. The integer portion has a number of bits corresponding to the number of select lines SEL, and thus corresponding to the number of clock phases output by PLL 125. The fractional portion provides additional resolution in the selection of the time-averaged frequency of the output clock signal on line COUT. Adder 138 adds the digital value on lines FREQ with a feedback value from the current output of register 140, and applies this sum to register 140, which is clocked by the output of multiplexer 134. The output of the integer portion of register 140 drives lines SEL applied to multiplexer 134, while the outputs of the integer register and the fraction register of register 140 are together combined into a ten-bit value that is applied back to adder 138 as feedback. In this way, adder 138 adds the current contents of register 140, which includes the current phase selection state applied to multiplexer 134 on lines SEL, to the frequency selection value on lines FREQ, for use in the selection of the next clock phase.
Phase synthesis circuit 129 includes multiplexer 144 which receives the multiple phases generated by PLL 125, and forwards a phase, selected by the digital value on lines SELPH, to the clock input of D-type flip-flop 146. The D input of flip-flop 146 receives the non-inverting output of flip-flop 136 in frequency synthesis circuit 127, and generates the output clock signal on line CSHOUT from its inverting output. Lines SELPH are generated from register 143, which receives a value from adder 142 corresponding to the sum of the current value of lines SEL of frequency synthesis circuit 127 and a digital input value presented on lines PHASE from control circuitry elsewhere within the device.
In operation, the digital value on lines FREQ thus corresponds to the number of phases output from PLL 125 that are to elapse between successive edges of the output clock signal on line COUT. The fractional component of this value provides additional precision in the average output frequency, because these fractional values accumulate and carry in such a manner as to modulate the integer output on lines SEL, and thus modulate the position of the clock edges selected by multiplexer 134. The digital value on lines PHASE indicating the desired phase relationship between the clock signals on lines COUT, CSHOUT is added by adder 142 with the current value of the phase presented on lines SEL; the resulting sum is stored in register 143 and is presented to multiplexer 144 on lines SELPH. Multiplexer 144 then selects the corresponding phase from PLL 125 for application to the clock input of flip-flop 146. Upon the rising transition of this selected clock phase, flip-flop 146 stores the current contents of flip-flop 136 (non-inverted) and applies this state at its inverting output on line CSHOUT.
FIG. 2 illustrates another example of one of the frequency synthesis circuits described in the Mair and Xiu article. In FIG. 2, frequency synthesis circuit 152 generates a clock signal in a pipelined manner, by way of separate paths 152a, 152b for generating the leading and trailing edges of an output clock signal on line COUT. Each of paths 152a, 152b includes a respective thirty-two to one multiplexer 154a, 154b for selecting one of the thirty-two equally-spaced clock phases output by a voltage controlled oscillator (VCO) in a conventional phase-locked loop (PLL) (not shown). Digital select signals, for selecting the corresponding phase, are presented on lines SELa, SELb, from accumulator 150 and adder 160, respectively. In this example, therefore, sixty-four potential phases are available for use in the generation of the output clock signal on line COUT, requiring six integer bits to select among the potential phases. According to this preferred embodiment of the invention, an input digital signal on lines FREQ selects the output frequency, with the most significant five bits FREQ[32:28] forwarded, via adder 159, to adder 160 in path 152b to generate the trailing edge of the output clock signal, and with the thirty-two least significant bits FREQ[31:0] forwarded to accumulator 150 in path 152a. Adder 159 determines the duty cycle of the output clock by adding a five-bit value received on lines DUTY to the most significant bits of lines FREQ. The output of adder 159 is then applied to adder 160, for generation of the trailing edge of the output clock signal.
In this conventional circuit, the outputs of multiplexers 154a, 154b are to corresponding NAND gates 155a, 155b, respectively. The outputs of NAND gates 155a, 155b are applied to the clock inputs of D-flip-flops 156a, 156b, which are connected in toggle fashion as shown. The outputs of flip-flop 156a, 156b are forwarded to inputs of exclusive-OR gate 158a and exclusive-NOR gate 158b, which drive clock phases CLKa, CLKb, respectively. Line CLKa is connected to a second input of NAND gate 155a and to a clock input of adder 160, and line CLKb is connected to a second input of NAND gate 155b and to clock inputs of accumulator 150 and adder 160.
In path 152a, multiplexer 154a is controlled by lines SELa generated by accumulator 150; similarly, in path 152b, multiplexer 154b is controlled by lines SELb generated by adder 160. Each of accumulator 150 and adder 160 are constructed in a pipelined fashion, so that accumulator 150 is performing the appropriate operations to generate its next value on lines SELa during such time as the trailing edge of the clock signal on line COUT is being generated by path 152b, and so that adder 160 is generating its next value for lines SELb during such time as the leading edge of the clock signal on line COUT is propagating through path 152a. Paths 152a, 152b are synchronized by line D2U, which effectively communicate the value on lines SELa from accumulator 150 to adder 160.
Pipelined accumulator 150 generates a five-bit integer result and a twenty-seven bit fraction result, based on the sum of its current contents and the least significant bits of signal FREQ. The integer result is output on select lines SELa to multiplexer 154a, is also forwarded to adder 160 on lines D2U, and is combined with the fraction result to be added in the next cycle. Pipelined adder 160 receives the five most significant lines FREQ [32:28] (via adder 159) and adds this value with the integer received from accumulator 150 on lines D2U, to determine the value on lines SELb applied to multiplexer 154b in path 152b. Each of accumulator 150 and adder 160 is preferably pipelined so that each has one full cycle of output clock time to finish its respective function.
In operation, control circuitry elsewhere within the integrated circuit in which frequency synthesis circuit 152 presents a digital word on lines FREQ indicating the frequency at which the clock signal on line COUT is to be generated by indicating the number of phases of the PLL output between adjacent edges of the output clock. The digital word on lines FREQ has both an integer portion and a fraction portion which together set the time-averaged frequency of the clock signal on line COUT; optionally, a duty cycle selection value on lines DUTY to adder 159. During generation of the leading edge of the output clock signal, line CLKa is high to enable the output of multiplexer 154a to toggle flip-flop 156a, during which time line CLKb is low. Lines CLKa, CLKb are necessarily complementary to one another, considering that exclusive-OR gate 158a and exclusive-NOR gate 158b receive the same inputs but generate opposite output states relative to one another. During such time as the rising edge of the output clock is being generated through path 152a, path 152b is updating the value of its selection integer to be applied to multiplexer 154b on lines SELb. During the time that line CLKa is high and line CLKb is low, the output of NAND gate 155b is forced high, blocking pulses from multiplexer 154b from affecting the state of flip-flop 156b. At this time, the output of accumulator 150 is applied to multiplexer 154a to select a corresponding VCO phase which, on its trailing edge, causes NAND gate 155a to make a low-to-high transition, toggling flip-flop 156a to now match the output of flip-flop 156b (these states being complementary previously). This toggling causes the output of exclusive-OR gate 158a to make a high-to-low transition, and also causes the output of exclusive-NOR gate 158b to make a low-to-high transition, thus issuing a rising edge of the output clock on line COUT and driving line CLKb from low to high. Line CLKa is of course driven low by exclusive-OR gate 158a, locking out NAND gate 155a from responding to the output of multiplexer 154a. 
Once line CLKa is low and line CLKb is high, path 152b selects the phase from VCO 30 for use in generating the trailing edge on line COUT, by operation of multiplexer 154b. During this time in which line CLKa is low, blocking transitions from multiplexer 154a from toggling flip-flop 156a, accumulator 150 is updating its contents for the next cycle. The next trailing edge of this phase is then passed to NAND gate 155b which, because line CLKb is now high, toggles the state of flip-flop 156b, causing its output to now differ from that of flip-flop 156a. This state causes exclusive-NOR gate 158b to drive line COUT low again, along with line CLKb. These same inputs cause exclusive-OR gate 158a to drive a low-to-high transition at its output on line CLKa, ending the cycle.
The circuits of FIGS. 1 and 2, which are described in the Mair and Xiu article, provide important improvements in the generation of clock signals in integrated circuits, including precise selection of clock frequencies with minimal drift, with performance suitable for applications requiring extremely high frequency accuracy. However, certain limitations are present in each of these circuits.
One such limitation is present in the circuit of FIG. 1, as a result of multiplexers 134, 144. Each of these multiplexers are m-to-one multiplexers, with m being greater than two (e.g., thirty-two in the example described in the Mair and Xiu article). It has been observed that these m-to-one multiplexers are vulnerable to the generation of “glitches” upon switching, because of the multiple-bit select values. For example, a 32-to-1 multiplexer 134 requires a five-bit select value. The worst case for glitch generation occurs with all five bits switching simultaneously from one selection to another, for example from 000002 to 111112. Because there can be no guarantee that all five bits will be switched by registers 140, 143 at exactly the same instant, it is entirely likely that an intermediate value (e.g., 101102) could be applied to multiplexers 134, 144 for a finite period of time. If multiplexers 134, 144 respond quickly enough, or if the skew is long enough, this intermediate select value can result in the application of the corresponding VCO output to the clock input of the corresponding flip-flop 136, 146, causing an unwanted toggling of clock signals COUT, CSHOUT. The circuit of FIG. 1 is therefore vulnerable to inaccuracy in some instances, especially as the operating frequency is increased.
In addition, still referring to the circuit of FIG. 1, all possible phase shifts (0° to 360°) are not available for the phase differential between the clock signals on lines COUT and CSHOUT. Instead a “dead zone” of unavailable phase shifts is necessarily present, because of the non-zero propagation delay of adder 142. Values on lines PHASE corresponding to phase shifts that are within this propagation delay, from the non-shifted output on line COUT, will not propagate to multiplexer 144 in time to clock out a proper signal on line CSHOUT.
It has also been observed that the performance of the circuit of FIG. 2 has certain timing constraints. In particular, relationships between the propagation delays of the two paths 152a, 152b result from their interlocking nature. As described in the Mair and Xiu article, the sum of the clock-to-output delay of the final register in accumulator 150 plus the decode delay of multiplexer 154a plus the propagation delay of multiplexer 154a itself is the lower limit of the time duration between a rising edge of the output clock and the next falling edge. Similarly, the sum of the propagation delay of gate 155a plus the clock-to-output delay of flip-flop 156a plus the propagation delay of gate 158a is the lower limit of the time duration between the falling edge of the output clock and its next rising edge. While proper design may provide good performance for this circuit, these propagation delay sums limit the ultimate clock speed of the circuit. Other limitations in the performance of this circuit arise from propagations delay through accumulator 150, especially because of its large size. This circuit, because of its thirty-two-to-one multiplexers 154a, 154b, is also vulnerable to glitches as discussed above.